Heterojunction field effect transistors that are capable of operating at relatively low temperatures and at extremely fast switching times such as less than 10 picoseconds have been suggested. Such FET devices have been referred to as High Electron Mobility Transistors (HEMT). The high switching speed obtainable is due to the high channel mobility at relatively low temperatures.
For instance, such heterojunction field effect transistors are reported in Japanese Journal of Applied Physics, Volume 19, No. 5, May 1980, pp. L225-L227, "A New Field-Effect Transistor With Selectively Doped GaAs/N-Al.sub.x Ga.sub.1-x As Heterojunctions"by Mimura, et al. The device suggested therein includes a pair of undoped gallium arsenide layers sandwiching a layer of silicon doped gallium aluminum arsenide. A rectifying contact for the gate is provided by deposition of aluminum on the surface of the non-doped gallium arsenide of the top layer. Such devices, however, could stand improvement with respect to the threshold voltage in not being as controllable as desired. Devices with controllable, low threshold voltages are essential for logic circuits having reduced power supply voltages. To the extent that a Schottky or rectifying contact to the gate is employed, a critically designed doped layer is required to obtain a near zero threshold voltage.
Hiyamizo, et al., "Extremely High Mobility of 2-Dimensional Electron Gas in Selectively Doped GaAs/N-AlGaAs Heterojunction Structures Grown by MBE", Japanese Journal of Applied Physics, Volume 20, No. 4, Apr. 1981, pp. L245-L248 report a selectively doped heterojunction structure wherein an undoped gallium aluminum arsenide layer is deposited on top of an undoped gallium arsenide layer. A silicon doped gallium aluminum arsenide layer is disposed over the undoped gallium aluminum arsenide layer and an ohmic contact is made by applying Au-Ge to the contact areas including the mesa edges where the GaAs/N-AlGaAs interface is exposed. This structure is primarily to investigate the accumulation of a two-dimensional electron gas at the interface of the heterojunction. Also suggested therein is an Enhancement Mode High Electron Mobility Transistor (E-HEMT) that incorporates an undoped gallium arsenide layer; an undoped gallium aluminum arsenide layer; and a silicon doped gallium aluminum arsenide layer. Ohmic contacts are applied to the source and drain regions, and an aluminum Schottky gate is applied to the silicon doped gallium aluminum arsenide upper layer. The threshold voltage exhibited for such device at room temperature was zero and at 77.degree. C was 0.19 volts. While such arrangement exhibits a threshold voltage that lies near zero, the characteristics of the device are not very controllable in that very stringent control of both layer thickness and doping level is required to obtain the desired threshold voltage. This type of extreme care is undesirable and should be avoided in production processes where high yields are required.
U.S. Pat. No. 4,151,635 to Kashkooli, et al. suggests a P-channel MOS device formed in a first region and an N-channel MOS device formed in a second region. Each of the P-channel and N-channel devices has a polycrystalline silicon gate structure in which the polycrystalline silicon material is doped with a P-type impurity to make possible the matching of the threshold voltages of both of the devices. Such devices are insulated gate field effect transistors.
U.S. Pat. No. 4,075,652 to Umebachi, et al. suggests a heterojunction type GaAs junction field effect transistor. The channel region consists of an N-type gallium arsenide layer with a higher mobility and a gate region that consists of a P-type gallium arsenide layer that is grown heteroepitaxially. The gate, source, and drain regions are self-aligned and the drain electrodes are formed of a metal such as aluminum. The gate junction is provided by the P-N junction between the first and second layers and the conductivity in the first layer is controlled by the electric field in the second layer. A third layer of the same conductivity type as the second layer forms an extension of the second layer and an ohmic contact of aluminum is formed on the gate extension.
Umebachi, et al., "A New Heterojunction Gate GaAs FET", IEEE Transaction on Electron Devices", August 1975, p. 613, suggests a structure that is similar to the one in U.S. Pat. No. 4,075,652 wherein source, drain, and gate contacts of gold-germanium eutectic are employed. U.S. Pat. No. 4,583,105 issued Apr. 15, 1986 to Rosenberg, disclosure of which is incorporated herein by reference, discloses a heterojunction field effect transistor having a threshold voltage that lies near zero volts. The heterojunction field effect transistor disclosed therein employs a semiconductor gate to which an ohmic contact can be made.
In particular, the device disclosed in U.S. Pat. No. 4,583,105 is concerned with a double heterojunction field effect transistor that utilizes a substrate on which a first layer of single crystal semiconductor material such as gallium arsenide or germanium is epitaxially deposited. Such also employs a barrier element of a single crystal semiconductor material such as gallium aluminum arsenide that forms a heterojunction with the first layer. The band energy difference between the latter and the barrier element has a given barrier height. Means are disposed on the barrier element for controlling at least the band edge of the first layer adjacent the heterojunction so that it lies near the fermi level. The means has the same potential as the source and, relative to the barrier element, has a barrier height equal to the given barrier height. The means for controlling includes a single crystal semiconductor gate of a III-IV compound such as gallium arsenide to which an ohmic contact can be made as a result of its heavy N-conductivity type doping. In addition, the device disclosed in said patent application has a semiconductor gate to which an ohmic contact such as gold-germanium can be made. The double heterojunction transistor device therein is an enhancement mode device which, in the absence of any doping in its barrier layer, has a threshold voltage which normally lies near zero.